Custom 8-bit CPU

Three weeks, a bench full of discrete logic, and a mandate to understand computers from the transistor up. Working with Windy City Labs at CTD Northwestern, I engineered an 8-bit CPU: defining the instruction set, wiring the control logic, and validating everything with a bespoke assembler.

Hardware architecture

• Harvard-style data path with dedicated instruction and data memory, microcoded control ROM, and tri-state bus arbitration.
• Custom ISA featuring 16 opcodes (ALU, branch, memory, IO) with single-cycle execution for arithmetic and pipelined micro-ops for memory access.
• PLA-driven control unit that sequences clock phases, manages register enables, and stabilises asynchronous inputs from the front-panel switches.

Tooling & validation

• KiCad schematics + PCB layouts for the ALU, register file, and clock generator; SPICE checks confirmed timing margins before fabrication.
• Wrote a Python assembler that emits hex suitable for the EEPROM burner; added macros for loops and immediate constants to speed prototyping.
• Oscilloscope + logic analyser sessions captured micro-instruction traces, letting me tune propagation delay and debounce timing.

Teaching impact

• Delivered lightning talks to other cohorts to explain opcodes, address modes, and why the flag register matters for branching.
• Produced lab notes and test programs (Fibonacci, LED chaser, mini calculator) so future students can extend the platform.